AN2839 datasheet(7/40 Pages) STMICROELECTRONICS

7 / 40 page

AN2839

Designing an application with L6228

Doc ID 15104 Rev 1

7/40

Equation 3

always assuming that the power supply does not recharge the capacitor, and neglecting the

output current ripple and the dead-time. Usually (if C > 100 µF) the capacitance role is much

less than the ESR, in which case the supply voltage ripple can be estimated as:

Equation 4

Equation 5

For example, if a maximum ripple of 500 mV is allowed and IOUT = 1 A, the capacitor ESR

should be lower than:

Equation 6

Equation 7

In fact, current sunk by the VSA and VSB pins of the device is subject to higher peaks due to

the reverse recovery charge of the internal freewheeling diodes. The duration of these

peaks is very short and can be filtered using a small value (100÷200 nF), good-quality

ceramic capacitor connected as close as possible to the VSA, VSB and GND pins of the IC.

The bulk capacitor should be chosen with a maximum operating voltage 25% greater than

the maximum supply voltage, considering also the power supply tolerances. For example,

with a 48 V nominal power supply with 5% tolerance, the maximum voltage will be 50.4 V,

and the operating voltage for the capacitor should be at least 63 V.

1.4

Layout considerations

Working with devices that combine high-power switches and control logic in the same IC,

special attention has to be paid to the layout of the PCB. In extreme cases, Power DMOS

commutation can induce noise that may cause improper operation in the logic section of the

device. Noise can be radiated by high dV/dt nodes or high dI/dt paths, or conducted through

GND or supply connections. Logic connections, especially high-impedance nodes (actually

all logic inputs, see Section 1.9), must be kept far from switching nodes and paths. With the

L6228 in particular, the external components for the charge-pump circuitry should be

connected together through short paths, since these components are subject to voltage and

current switching at a relatively high frequency (600 kHz). The primary means of minimizing

conducted noise is to work on a good GND layout (see Figure 5 on page 8).

OUT

2ESR

⋅

OFF

--------------------------------

⎝⎠

⎛⎞

⋅

OUT

ESR

⋅

OUT

ESR

⋅⋅

ESR

0.5V

------------

500m

in slow decay

in fast decay

ESR

---

0.5V

------------

⋅

250m

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