ST10F27x PLL jitter effect in CAN protocol

AN2352

18/20

3.1.2

Examples

In the first example of

Section 1.6, the frequency of the CAN module clock was 20 MHz,

BRP = 1 and the bit rate 1 Mbit/s. Using the

Figure 5 on page 16, it follows that

so the clock tolerance range is reduced by

becoming 0.37%.

Using the range reduction formula calculated in the previous section:

In the second example, the frequency of CAN module clock was 32 MHz, BRP = 31 and the

bit rate 100 Kbit/s. Using the

Figure 5 on page 16, it follows that

so the clock tolerance range is reduced by

which is negligible compared to the original value of 1.58%.

In fact, using the range reduction formula calculated in the previous section:

3.2

Conclusion

Given the characteristics of the ST10F27x PLL, in most configurations the PLL can be used

and it fulfills the CAN standard requirements.

δPLL 13 10 tq

⋅⋅

520

tCPU

⋅

=

()

3ns

=

2

δPLL

⋅

()

213

tBT tPB2

–

⋅

()

⋅

()

----------------------------------------------------------------

0.006

µs

213

1

µs0.2µs

–

⋅

()

⋅

------------------------------------------------------------

0.02%

==

df

dfPLL

–

df

----------------------------

6

100

----------

0.06

6%

==

=

δPLL 13 10 tq

⋅⋅

4160

tCPU

⋅

=

()

4.5ns

=

2

δPLL

⋅

()

213

tBT tPB2

–

⋅

()

⋅

()

----------------------------------------------------------------

0.009

µs

213

10

µs4µs

–

⋅

()

⋅

-----------------------------------------------------------

0.0035%

==

df

dfPLL

–

df

----------------------------

9

4000

-------------

0.00225

0.225%

==

=