AN2352

Configuration of the CAN bit timing

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Figure 4.

Structure of the CAN Core’s CAN Protocol Controller

The data in the bit timing registers is the configuration input of the CAN protocol controller.

The Baud rate prescaler (whose value is configured by the BRP field of the bit timing

register) defines the length of the time quantum, the basic time unit of the bit time; the bit

timing logic (configured by TSEG1, TSEG2 and SJW) defines the number of time quanta in

the bit time.

The processing of the bit time, the calculation of the position of the sample point and

occasional synchronizations are controlled by the BTL state machine, which is evaluated

once each time quantum. The rest of the CAN protocol controller, the bit stream processor

(BSP) state machine, is evaluated once each bit time at the sample point.

The Shift Register serializes the messages to be sent and parallelizes received messages.

Its loading and shifting is controlled by the BSP.

The BSP translates messages into frames and frames into messages. It generates and

discards the enclosed fixed format bits, inserts and extracts stuff bits, calculates and checks

the CRC code, performs the error management and determines the type of synchronization

to be used. It is evaluated at the sample point and processes the sampled bus input bit. The

time needed to calculate the next bit to be sent after the sample point (for example, data bit,

CRC bit, stuff bit, error flag or idle) is called the information processing time (IPT).

length is the lower limit of the programmed length of Phase_Seg2. In case of a

synchronization, Phase_Seg2 may be shortened to a value less than IPT, which does not

affect bus timing.

Sample_point

Bit_to_send

Sync_mode

Bus_off

Scaled_clock (tq)

System clock

Receive_data

Transmit_data

Control

Received_message

Send_message

Status

Bit

timing

logic

Baud rate

prescaler

Sampled_bit

Configuration (TSEG1, TSEG2, SJW)

Configuration (BRP)

Shift register

Received_data_bit

Next_data_bit

Control