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AN2352 bảng dữ liệu(PDF) 16 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  PLL jitter effects on C-CAN modules of the ST10F27x
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Phase locked loop (PLL)
AN2352
16/20
Device noise of the circuit in the PLL
Long term jitter is inversely proportional to the bandwidth of the PLL: The wider the loop
bandwidth, the lower the jitter due to noise in the loop. Moreover, long term jitter is
practically independent of the multiplication factor.
The most noise sensitive circuit in the PLL circuit is definitely the VCO (voltage controlled
oscillator). There are two main sources of noise: thermal (random noise, frequency
independent thus practically white noise) and flicker (low frequency noise). These two noise
sources lead to a jitter as illustrated in
Figure 5. This figure shows three distinctive zones:
–
the first zone in which the R.M.S. value of the accumulated jitter is
proportional to
the square root of N, where N is the number of clock periods within the considered
time interval,
–
the second zone in which the R.M.S. value of the accumulated jitter is
proportional
to N and,
–
the third zone where for a large value of N, a saturation effect is evident, so the
jitter does not grow anymore when considering a longer time interval (jitter stable
increasing the number of clock periods N). The saturation value corresponds to
what has been called self referred long term jitter of the PLL. In
Figure 5 the
maximum jitter trend versus the number of clock periods N (for some typical CPU
frequencies) is reported: The curves represent the very worst case, computed
taking into account all corners of temperature, power supply and process
variations; the real jitter is always measured well below the given worst case
values.
Noise in supply and substrate
Digital supply noise adds determining elements to PLL output jitter, independent of the
multiplication factor. Its effect is strongly reduced thanks to particular care used in the
physical implementation and integration of the PLL module inside the device. In any case,
the contribution of digital noise to global jitter is widely taken into account in the curves
provided in
Figure 5.
Figure 5.
ST10F27x PLL jitter
N (CPU clock periods)
200
400
±5
±1
800
600
1000
1200
0
0
±2
±3
±4
24 MHz
40 MHz
32 MHz
16 MHz
TJIT
64 MHz
1400



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