AN2352 datasheet(14/20 Pages) STMICROELECTRONICS

14 / 20 page

Configuration of the CAN bit timing

AN2352

14/20

1.6.2

Example for bit timing at low baud rate

In this example, CPU clock frequency is 64 MHz, the frequency of CAN module clock is

32 MHz, BRP is 31 and the bit rate is 100 Kbit/s. By default, the ST10F27x divides by 2 the

clock that feeds the CAN cells (mandatory when the CPU clock frequency is higher than

40 MHz). It is possible to disable this function by setting bit 2 of the XMISC register.

In this example, the concatenated bit time parameters are (4-1)3 and (5-1)4 and (4-1)2 and

(31)6 and the bit timing register is programmed to = 0x34DF.

1 µs

= 32 x tCAN_CLK

delay of bus driver

200 ns

delay of receiver circuit

80 ns

delay of bus line (40m)

220 ns

tProp

1 µs

= 1 x tq

tPB1

4 µs

= 4 x tq

tTSeg1

5 µs

= tProp + tPB1

tTSeg2

4 µs

= Information Processing Time + 3 • tq

tSJW

4 µs

= 4 x tq

tSync-Seg

1 µs

= 1 x tq

bit time

10 µs

= tSync-Seg + tTSeg1 + tTSeg2

tolerance for CAN clock

= 1.58%

min

min PB1 PB2

)

bit_time

⋅

PB2

–

()

⋅

-----------------------------------------------------------------------

tSJW

()

210

tBT

⋅⋅

----------------------------------

⎝⎠

⎛⎞

min PB1 PB2

(,)

bit_time

⋅

PB2

–

()

⋅

-----------------------------------------------------------------------

µs

213

µs4µs

–

⋅

()

⋅

-----------------------------------------------------------

1.58%

tSJW

()

210

tBT

⋅⋅

----------------------------------

µs

210

µs

⋅

()

⋅

------------------------------------------

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