HDM8513 datasheet(36/67 Pages) HYNIX

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5. Signal Description

5.1 Inputs

XTAL1

XTAL1 can be configured either for sampling clock input or PLL

reference clock input . The sampling clock rate must be a minimum of

1.33 times the symbol rate of the signal to be processed and at least

equal to the total bandwidth of the signal to be processed.

RESET

A low on this signal causes the chip to be initialized. I/O registers are

not cleared by this signal. This signal is asynchronous with respect to

the clock.

AIN_I

Analog Input Signal for I channel. This should be AC coupled with

Analog Input Source via 0.1uF capacitor.

AIN_Q

Analog Input Signal for I channel. This should be AC coupled with

Analog Input Source via a 0.1uF capacitor.

5.2 Outputs

VTOP

Top Reference Voltage Output of about 2.0V. It should be bypassed to

GND by 0.1uF capacitor. External bias voltage can be applied if

necessary.

VBOT

Bottom Reference Voltage Output of 1.0V. It should be bypassed to

GND by a 0.1uF capacitor. External bias voltage can be applied if

necessary.

REF_I

Middle Reference Voltage for I Channel. It should be bypassed to GND

by a 0.1uF capacitor.

REF_Q

Middle Reference Voltage for Q Channel. It should be bypassed to

GND by a 0.1uF capacitor.

DATA [7:0]

The eight bit output data is provided in parallel format to be handed to

an MPEG decoder for video and audio decompression.

HDM8513 bảng dữ liệu(PDF) 36 Page - Hynix Semiconductor