HDM8513 datasheet(29/67 Pages) HYNIX

tên linh kiện	HDM8513

Giải thích chi tiết về linh kiện	DVB/DSS Compliant Receiver

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3.7 Clock Generation PLL

An integrated VCO is locked to MxN times a reference frequency provided by a external clock.

int_clk

ext_clk

1/M

1/2

1/N

enable

PLL Analog Core

FRef

FFb

Reference

Divider

Feedback

Divider

FIGURE 20: CLOCK SIGNAL GENERATION

This programmable PLL consists of a PLL analog core, a reference divider with a divider ratio M, a

feedback divider with a divider ratio N, and a divider which askes the duty cycle 1/2.

Reference divider and feedback divider are used to synthesize various frequencies from a reference

frequency,

Since PLL synchronizes the frequency and phase of two signals, FRef and FFb,

Internal clock is calculated as follows

The following two PLL modes are provided to control PLL.

(1) PLL Enable mode : The internal clock is connected to the generated clock of the PLL.

(2) PLL Disable mode : The PLL is bypassed and the external clock is directly connected to the

internal clock.

More information can be found on the part of the write register.

fext_clk

fint_clk

fint_clk =

fext_clk

fext_clk.

HDM8513 bảng dữ liệu(PDF) 29 Page - Hynix Semiconductor