GMS87C1102 datasheet(66/89 Pages) HYNIX

66 / 89 page

GMS81C1102 / GMS81C1202

Jan. 2002 ver 2.0

21. Power Saving Mode

For applications where power consumption is a critical

factor, device provides three kinds of power saving func-

tions, STOP mode, Wake-up Timer mode and internal RC-

oscillated watchdog timer mode.

The power saving function is activated by execution of

STOP instruction after setting the corresponding bit

(WAKEUP, RCWDT) of CKCTLR.

Table 21-1 shows the status of each Power Saving Mode

Note: Before executing STOP instruction, clear all in-

terrupt request flag. Because if the interrupt re-

quest flag is set before STOP instruction, the MCU

runs as if it doesn’t perform STOP instruction, even

though the STOP instruction is completed. So insert

two lines to clear all interrupt request flags (IRQH,

IRQL) before STOP instruction as shown each ex-

ample.

21.1 Stop Mode

In the Stop mode, the on-chip oscillator is stopped. With

the clock frozen, all functions are stopped, but the on-chip

RAM and Control registers are held. The port pins out the

values held by their respective port data register, port di-

rection registers. Oscillator stops and the systems internal

operations are all held up.

• The states of the RAM, registers, and latches valid

immediately before the system is put in the STOP

state are all held.

• The program counter stop the address of the

instruction to be executed after the instruction

“STOP” which starts the STOP operating mode.

The Stop mode is activated by execution of STOP in-

struction after setting the bit WAKEUP and RCWDT

of CKCTLR to “00”. (This register should be written

by byte operation. If this register is set by bit manipu-

lation instruction, for example “set1” or “clr1” instruc-

tion, it may be undesired operation)

In the Stop mode of operation, VDD can be reduced to min-

imize power consumption. Care must be taken, however,

to ensure that VDD is not reduced before the Stop mode is

invoked, and that VDD is restored to its normal operating

level, before the Stop mode is terminated.

The reset should not be activated before VDD is restored to

its normal operating level, and must be held active long

enough to allow the oscillator to restart and stabilize.

Note: After STOP instruction, at least two or more NOP

instruction should be written

Ex)

LDM CKCTLR,#0000_1110B

LDM IRQH,#0

LDM IRQL,#0

STOP

NOP

In the STOP operation, the dissipation of the power asso-

ciated with the oscillator and the internal hardware is low-

ered; however, the power dissipation associated with the

pin interface (depending on the external circuitry and pro-

gram) is not directly determined by the hardware operation

of the STOP feature. This point should be little current

flows when the input level is stable at the power voltage

Peripheral

STOP

Wake-up Timer

Internal RC-WDT

RAM

Retain

Control Registers

Retain

I/O Ports

Retain

CPU

Stop

Timer0

Stop

Operation

Stop

Oscillation

Stop

Oscillation

Stop

Prescaler

Stop

÷ 2048 only

Stop

Internal RC oscillator

Stop

Oscillation

Entering Condition

CKCTLR[6,5]

Power Saving Release

Source

RESET, INT0, INT1

RESET, INT0, INT1,

Timer0

RESET, INT0, INT1,

RC-WDT

Table 21-1 Power Saving Mode

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