GMS87C1102 datasheet(63/89 Pages) HYNIX

63 / 89 page

GMS81C1102 / GMS81C1202

Jan. 2002 ver 2.0

19.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction,

which has the lowest priority order.

Interrupt vector address of BRK is shared with the vector

of TCALL 0 (Refer to Program Memory Section). When

BRK interrupt is generated, B-flag of PSW is set to distin-

guish BRK from TCALL 0.

Each processing step is determined by B-flag as shown in

Figure 19-4.

Figure 19-4 Execution of BRK/TCALL0

19.3 Multi Interrupt

If two requests of different priority levels are received si-

multaneously, the request of higher priority level is ser-

viced. If requests of the interrupt are received at the same

time simultaneously, an internal polling sequence deter-

mines by hardware which request is serviced.

However, multiple processing through software for special

features is possible. Generally when an interrupt is accept-

ed, the I-flag is cleared to disable any further interrupt. But

as user sets I-flag in interrupt routine, some further inter-

rupt can be serviced even if certain interrupt is in progress.

Example: Even though Timer1 interrupt is in progress,

INT0 interrupt serviced without any suspend.

TIMER1:

PUSH

LDM

IENH,#80H

;

Enable INT0 only

LDM

IENL,#0

;

Disable other

;

Enable Interrupt

LDM

IENH,#0FFH

;

Enable all interrupts

LDM

IENL,#0F0H

POP

RETI

Figure 19-5 Execution of Multi Interrupt

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

enable INT0

TIMER 1

service

INT0

service

Main Program

service

Occur

TIMER1 interrupt

Occur

INT0

disable other

enable INT0

enable other

In this example, the INT0 interrupt can be serviced without any

pending, even TIMER1 is in progress.

Because of re-setting the interrupt enable registers IENH,IENL

and master enable "EI" in the TIMER1 routine.

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