GMS87C1102 datasheet(64/89 Pages) HYNIX

64 / 89 page

GMS81C1102 / GMS81C1202

Jan. 2002 ver 2.0

19.4 External Interrupt

The external interrupt on INT0 and INT1 pins are edge

triggered depending on the edge selection register IEDS

(address 0E6H) as shown in Figure 19-6 .

The edge detection of external interrupt has three transition

activated mode: rising edge, falling edge, and both edge

Figure 19-6 External Interrupt Block Diagram

Example: To use as an INT0 and INT1

;

**** Set port as an input port RB2,RB3

LDM

RBIO,#1111_0011B

;

**** Set port as an interrupt port

LDM

RBFUNC,#0C0H

;

**** Set Falling-edge Detection

LDM

IEDS,#0000_0101B

Response Time

The INT0 and INT1 edge are latched into INT0IF and

INT1IF at every machine cycle. The values are not actually

polled by the circuitry until the next machine cycle. If a re-

quest is active and conditions are right for it to be acknowl-

edged, a hardware subroutine call to the requested service

routine will be the next instruction to be executed. The

DIV itself takes twelve cycles. Thus, a minimum of twelve

complete machine cycles elapse between activation of an

external interrupt request and the beginning of execution

of the first instruction of the service routine.

Below shows interrupt response timings.

Figure 19-7 Interrupt Response Timing Diagram

INT0IF

INT0 pin

INT0 INTERRUPT

INT1IF

INT1 pin

INT1 INTERRUPT

IEDS

[0E6H]

INT0 edge select

Ext. Interrupt Edge Selection

IEDS

ADDRESS : 0E6H

RESET VALUE : 00000000

00: Int. disable

01: falling

10: rising

11: both

INT1 edge select

00: Int. disable

01: falling

10: rising

11: both

Interrupt

goes

active

Interrupt

latched

Interrupt

processing

Interrupt

routine

8 fOSC

max. 12 fOSC

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