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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ML7344J bảng dữ liệu(PDF) 143 Page - List of Unclassifed Manufacturers |
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ML7344J bảng dữ liệu(HTML) 143 Page - List of Unclassifed Manufacturers |
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143 / 151 page  FEDL7344C/E/J-04 ML7344C/E/J 143/151 BANK1 Bit Address Symbol (# test register) 7 6 5 4 3 2 1 0 Description 0x00 BANK_SEL Register access bank select 0x01 CLK_OUT CLK_OUT (GPIOn) output frequency setting 0x02 TX_RATE_H TX data rate conversion setting (high 4 bits) 0x03 TX_RATE_L TX data rate conversion setting (low byte) 0x04 RX_RATE1_H RX data rate conversion setting 1 (high 4 bits) 0x05 RX_RATE1_L RX data rate conversion setting 1 (low byte) 0x06 RX_RATE2 RX data rate conversion setting 2 0x07 Reserved Reserved 0x08 ADC_CLK_SET RSSI ADC clock frequency setting 0x09-0A Reserved Reserved 0x0B PLL_LOCK_DETECT PLL lock detection setting 0x0C-0x12 Reserved Reserved 0x13 RSSI_MAG_ADJ Scale factor setting for ED value conversion 0x14 RSSI_VAL RSSI value indication 0x15 AFC_CTRL AFC control setting 0x16 CRC_POLY3 CRC Polynomial setting 3 0x17 CRC_POLY2 CRC Polynomial setting 2 0x18 CRC_POLY1 CRC Polynomial setting 1 0x19 CRC_POLY0 CRC Polynomial setting 0 0x1A PLL_DIV_SET PLL frequency division setting 0x1B TXFREQ_I TX frequency setting (I counter) 0x1C TXFREQ_FH TX frequency setting (F counter high 4 bits) 0x1D TXFREQ_FM TX frequency setting (F counter middle byte) 0x1E TXFREQ_FL TX frequency setting (F counter low byte) 0x1F RXFREQ_I RX frequency setting (I counter) 0x20 RXFREQ_FH RX frequency setting (F counter high 4 bits) 0x21 RXFREQ_FM RX frequency setting (F counter middle byte) 0x22 RXFREQ_FL RX frequency setting (F counter low byte) 0x23 CH_SPACE_H Channel space setting (high byte) 0x24 CH_SPACE_L Channel space setting (low byte) 0x25 SYNC_WORD_LEN SyncWord length setting 0x26 SYNC_WORD_EN SyncWord enable setting 0x27 SYNC_WORD1_SET0 SyncWord #1 setting (bit24 to 31) 0x28 SYNC_WORD1_SET1 SyncWord #1 setting (bit16 to 23) 0x29 SYNC_WORD1_SET2 SyncWord #1 setting (bit8 to 15) 0x2A SYNC_WORD1_SET3 SyncWord #1 setting (bit0 to 7) 0x2B SYNC_WORD2_SET0 SyncWord #2 setting (bit24 to 31) 0x2C SYNC_WORD2_SET1 SyncWord #2 setting (bit16 to 23) 0x2D SYNC_WORD2_SET2 SyncWord #2 setting (bit8 to 15) 0x2E SYNC_WORD2_SET3 SyncWord #2 setting (bit0 to 7) 0x2F FSK_CTRL GFSK/FSK modulation timing resolution setting |
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