ML7344J datasheet(140/151 Pages) ETC2

140 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

140/151

■Registers

●Register map

It is consist of 4 banks, BANK0, BANK1, BANK2 and BANK3. Each BANK has address space of 0x00 to 0x7F,

128 byte in total.

The space shown as gray highlighted part is not implemented in LSI or reserved bits. Reserved bits may be

assigned closed function. Please use default values to reserved bits, when write a register which contains reserved

bits. Regarding reserved register, access is inhibited. BANK3 is closed BANK, then access is limited..

Transition between banks can be controlled by bit 3-0 ( BANK[3:0] ) of [BANK_SEL] register.

: Implemented as functionable register

: Impelemted as reserved bits

BANK0

Bit

Address

Symbol

(# test register)

Description

0x00

BANK_SEL

0x01

RST_SET

Software reset setting

0x02

CLK_SET1

Clock configuration 1

0x03

CLK_SET2

Clock configuration 2

0x04

PKT_CTRL1

Packet configuration 1

0x05

PKT_CTRL2

Packet configuration 2

0x06

DRATE_SET

Data rate setting

0x07

DATA_SET1

TX/RX data configuration 1

0x08

DATA_SET2

TX/RX data configuration 2

0x09

CH_SET

RF channel setting

0x0A

RF_STATUS_CTRL

RF auto status transition control

0x0B

RF_STATUS

RF state setting and status indication

0x0C

DIO_SET

DIO mode configuration

0x0D

INT_SOURCE_GRP1

Interrupt status for INT0 to INT7

0x0E

INT_SOURCE_GRP2

Interrupt status for INT8 to INT15 (RX)

0x0F

INT_SOURCE_GRP3

Interrupt status for INT16 to INT23 (TX)

0x10

INT_EN_GRP1

Interrupt mask for INT0 to INT7

0x11

INT_EN_GRP2

Interrupt mask for INT8 to INT15

0x12

INT_EN_GRP3

Interrupt mask for INT16 to INT23

0x13

CRC_ERR_H

CRC error status (high byte)

0x14

CRC_ERR_M

CRC error status (middle byte)

0x15

CRC_ERR_L

CRC error status (low byte)

0x16

STATE_CLR

State clear control

0x17

TXFIFO_THRH

TX FIFO-Full level setting

0x18

TXFIFO_THRL

TX FIFO-Empty level setting and TX trigger level

setting in FAST_TX mode

0x19

RXFIFO_THRH

RX FIFO-Full level setting

0x1A

RXFIFO_THRL

RX FIFO-Empty level setting

0x1B

C_CHECK_CTRL

Control field (C-field) detection setting

0x1C

M_CHECK_CTRL

Manufacture ID field (M-field) detection setting

0x1D

A_CHECK_CTRL

Address field (A-Field) detection setting

0x1E

C_FIELD_CODE1

C-field setting code #1

0x1F

C_FIELD_CODE2

C-field setting code #2

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