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ML7344J bảng dữ liệu(PDF) 142 Page - List of Unclassifed Manufacturers |
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ML7344J bảng dữ liệu(HTML) 142 Page - List of Unclassifed Manufacturers |
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142 / 151 page ![]() FEDL7344C/E/J-04 ML7344C/E/J 142/151 BANK0 (continued) Bit Address Symbol (# test register) 7 6 5 4 3 2 1 0 Description 0x50 GPIO2_CTRL GPIO2 pin (pin #18) configuration setting 0x51 GPIO3_CTRL GPIO3 pin (pin #19) configuration setting 0x52 EXTCLK_CTRL EXT_CLK pin (pin #10) configuration setting 0x53 SPI/EX_PA_CTRL SPI interface IO configuration/external PA control setting 0x54 IF_FREQ_H IF frequency setting (high byte) 0x55 IF_FREQ_L IF frequency setting (low byte) 0x56-61 Reserved Reserved 0x62 OSC_ADJ1 Coarse adjustment of load capacitance for oscillation circuit 0x63 OSC_ADJ2 Fine adjustment of load capacitance for oscillation circuit 0x64-65 Reserved Reserved 0x66 RSSI_ADJ RSSI value adjustment 0x67 PA_MODE PA mode setting / PA regulator coarse adjustment 0x68 PA_REG_FINE_ADJ PA regulator fine adjustment 0x69 PA_ADJ PA gain adjustment 0x6A-6D Reserved Reserved 0x6E VCO_CAL VCO calibration setting or status indication 0x6F VCO_CAL_START VCO calibration execution 0x70 CLK_CAL_SET Low speed clock calibration control 0x71 CLK_CAL_TIME Low speed clock calibration time setting 0x72 CLK_CAL_H Low speed clock calibration result indication (high byte) 0x73 CLK_CAL_L Low speed clock calibration result indication (low byte) 0x74 Reserved 0x75 SLEEP_INT_CLR Interruption clear setting during SLEEP state 0x76 RF_TEST_MODE TX test pattern setting 0x77 STM_STATE State machine status / synchronization status indication 0x78 FIFO_SET FIFO readout setting 0x79 RX_FIFO_LAST RX FIFO data usage status indication 0x7A TX_PKT_LEN_H Tx packet length setting (high byte) 0x7B TX_PKT_LEN_L Tx packet length setting (low byte) 0x7C WR_TX_FIFO TX_FIFO 0x7D RX_PKT_LEN_H Rx packet length indication (high byte) 0x7E RX_PKT_LEN_L Rx packet length indication (low byte) 0x7F RD_FIFO FIFO read |
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