PRIXP425BD datasheet(40/112 Pages) INTEL

40 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Signal Descriptions

Datasheet

Table 14.

Oscillator Interface

Name

Power

Reset†

Type†

Description

OSC_IN

33.33-MHz, sinusoidal crystal input signal. Can be driven by an oscillator.

OSC_OUT

33.33-MHz, sinusoidal crystal output signal. Left disconnected when being

driven by an oscillator.

†

For a legend of the Type codes, see Table 4 on page 30.

Table 15.

GPIO Interface

Name

Power

Reset†

Type†

Description

GPIO[12:0]

I/O

General purpose Input/Output pins. May be configured as an input or an

output. As an input, each signal may be configured a processor interrupt.

Default after reset is to be configured as inputs.

Should be pulled low using a 10-K

Ω resistor when not being utilized in the

system.

GPIO[13]

I/O

General purpose input/output pins. May be configured as an input or an

output. Default after reset is to be configured as inputs.

Should be pulled low using a 10-K

Ω resistor when not being utilized in the

system.

GPIO[14]

I/O

Can be configured similar to GPIO Pin 13 or as a clock output. Configuration

as an output clock can be set at various speeds of up to 33.33 MHz with

various duty cycles. Configured as an input, upon reset.

Should be pulled low though a 10-K

Ω resistor when not being utilized in the

system.

GPIO[15]

CLKOUT

/VO

I/O

Can be configured similar to GPIO Pin 13 or as a clock output. Configuration

as an output clock can be set at various speeds of up to 33.33 MHz with

various duty cycles. Configured as an output, upon reset. Can be used to

clock the expansion interface, after reset.

Should be pulled low though a 10-K

Ω resistor when not being utilized in the

system.

†

For a legend of the Type codes, see Table 4 on page 30.

Table 16.

JTAG Interface

Name

Power

Reset†

Type†

Description

JTG_TMS

VI/PE

Test mode select for the IEEE 1149.1 JTAG interface.

JTG_TDI

VI/PE

Input data for the IEEE 1149.1 JTAG interface.

JTG_TDO

Output data for the IEEE 1149.1 JTAG interface.

JTG_TRST_N

VI/PE

Used to reset the IEEE 1149.1 JTAG interface.

The JTG_TRST_N signal must be asserted (driven low) during

power-up, otherwise the TAP controller may not be initialized properly,

and the processor may be locked.

When the JTAG interface is not being used, the signal must be pulled low

using a 10-K

Ω resistor.

JTG_TCK

Used as the clock for the IEEE 1149.1 JTAG interface.

†

For a legend of the Type codes, see Table 4 on page 30.

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