PRIXP425BD datasheet(22/112 Pages) INTEL

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Overview

Datasheet

2.1.10

High-Speed and Console UARTs

The UART interfaces are 16550-compliant UARTs with the exception of transmit and receive

buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the

16550 UART specification.

The interface can be configured to support speeds from 1,200 baud to 921 Kbaud. The interface

support configurations of:

• Five, six, seven, or eight data-bit transfers

• One or two stop bits

• Even, odd, or no parity

The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also are available

with the interface for hardware flow control.

2.1.11

GPIO

There are 16 GPIO pins supported by the IXP42X product line and IXC1100 control plane

processors. GPIO pins 0 through 13 can be configured to be general-purpose input or

general-purpose output. Additionally, GPIO pins 0 through 12 can be configured to be an interrupt

input.

GPIO Pin 14 can be configured similar to GPIO pin 13 or as a clock output. The output-clock

configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles. GPIO Pin 14

is configured as an input, upon reset.

GPIO Pin 15 can be configured similar to GPIO pin 13 or as a clock output. The output-clock

configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles. GPIO Pin 15

is configured as a clock output, upon reset. GPIO Pin 15 can be used to clock the expansion

interface, after reset.

2.1.12

Internal Bus Performance Monitoring Unit (IBPMU)

The IXP42X product line and IXC1100 control plane processors consists of seven 27-bit counters

that may be used to capture predefined durations or occurrence events on the North AHB, South

AHB, or SDRAM controller page hits/misses.

2.1.13

Interrupt Controller

The IXP42X product line and IXC1100 control plane processors consists of 32 interrupt sources to

allow an extension of the Intel XScale® Core FIQ and IRQ interrupt sources. These sources can

originate from some external GPIO pins or internal peripheral interfaces.

The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled. The

interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining interrupts are prioritized

in ascending order. For example, Interrupt 8 has a higher priority than 9, 9 has a higher priority than

10, and 30 has a higher priority that 31.

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