PRIXP425BD datasheet(100/112 Pages) INTEL

100 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Electrical Specifications

100

Datasheet

NOTES:

1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for

the address phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product

Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold

the address phase for at least one clock pulse after the HRDY is de-active.

2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks

for setup phase.

3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks

for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel® IXP4XX Product

Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold

the data setup phase for at least one clock pulse after the HRDY is de-active

4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the

Expansion Bus interface.

5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3

until HRDY is de-active

6. One cycle is the period of the Expansion Bus clock.

7. Timing tests were performed with a 70-pF capacitor to ground.

NOTES:

1. The Setup and Hold Timing Values are for all modes.

Table 58.

Setup/Hold Timing Values

Parameter

Min.

Max. Units

Notes

Output Valid.

Output Hold

Input Setup

Input Hold.

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