PRIXP425BD datasheet(35/112 Pages) INTEL

35 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Signal Descriptions

Datasheet

Table 8.

High-Speed, Serial Interface 1

Name

Power

Reset†

Reset† Type†

Description

HSS_TXFRAME1

I/O

The High-Speed Serial (HSS) transmit frame signal can be configured as

an input or an output to allow an external source to be synchronized with

the transmitted data. Often known as a Frame Sync signal. Configured as

an input upon reset.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

HSS_TXDATA1

O/D

Transmit data out. Open Drain output.

Must be pulled high with a 10-K

Ω resistor to VCCP.

HSS_TXCLK1

I/O

The High-Speed Serial (HSS) transmit clock signal can be configured as

an input or an output. The clock can be a frequency ranging from 512 KHz

to 8.192 MHz. Used to clock out the transmitted data. Configured as an

input upon reset. Frame sync and Data can be selected to be generated

on the rising or falling edge of the transmit clock.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

HSS_RXFRAME1

I/O

The High-Speed Serial (HSS) receive frame signal can be configured as

an input or an output to allow an external source to be synchronized with

the received data. Often known as a Frame Sync signal. Configured as an

input upon reset.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

HSS_RXDATA1

Receive data input. Can be sampled on the rising or falling edge of the

receive clock.

Should be pulled low through a 10-K

Ω resistor when not being utilized in

the system.

HSS_RXCLK1

I/O

The High-Speed Serial (HSS) receive clock signal can be configured as

an input or an output. The clock can be from 512 KHz to 8.192 MHz. Used

to sample the received data. Configured as an input upon reset.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

†

For a legend of the Type codes, see Table 4 on page 30.

Table 9.

MII Interfaces (Sheet 1 of 2)

Name

Power

Reset†

Reset† Type†

Description

ETH_TXCLK0

ZVI

Externally supplied transmit clock.

•

25 MHz for 100-Mbps operation

•

2.5 MHz for 10 Mbps

Should be pulled low through a 10-K

Ω resistor when not being utilized in

the system.

ETH_TXDATA0[3:0]

Transmit data bus to PHY, asserted synchronously with respect to

ETH_TXCLK0.

ETH_TXEN0

Indicates that the PHY is being presented with nibbles on the MII

interface. Asserted synchronously, with respect to ETH_TXCLK0, at the

first nibble of the preamble and remains asserted until all the nibbles of a

frame are presented.

ETH_RXCLK0

ZVI

Externally supplied receive clock.

•

25 MHz for 100-Mbps operation

•

2.5 MHz for 10 Mbps

Should be pulled low through a 10-K

Ω resistor when not being utilized in

the system.

†

For a legend of the Type codes, see Table 4 on page 30.

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