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IO96NDB2V1 bảng dữ liệu(PDF) 149 Page - Microsemi Corporation |
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IO96NDB2V1 bảng dữ liệu(HTML) 149 Page - Microsemi Corporation |
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149 / 242 page ![]() ProASIC3L Low Power Flash FPGAs Revision 13 2-133 Table 2-213 • ProASIC3L CCC/PLL Specification CCC/PLL Operating at 1.5 V Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz Delay Increments in Programmable Delay Blocks 1, 2 1603 ps Serial Clock (SCLK) for Dynamic PLL 4 110 Number of Programmable Values in Each Programmable Delay Block 32 Input Period Jitter 1.5 ns CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter 1 Global Network Used 3 Global Networks Used 0.75 MHz to 24 MHz 0.50% 0.70% 24 MHz to 100 MHz 1.00% 1.20% 100 MHz to 250 MHz 1.75% 2.00 250 MHz to 350 MHz 2.50% 5.60% Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter5 LockControl = 0 1.6 ns LockControl = 1 0.8 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 0.6 5.56 ns Delay Range in Block: Programmable Delay 2 1, 2 0.025 5.56 ns Delay Range in Block: Fixed Delay 1, 2 2.2 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 for deratings. 2. TJ = 25°C, VCC = 1.5 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help for more information. 4. Maximum value obtained for a –1 speed grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-40 • Peak-to-Peak Jitter Definition Tperiod_max Tperiod_min Output Signal |
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