IO96NDB2V1 datasheet(147/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

2-131

Table 2-210 • A3PE3000L Global Resource – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter

Description

–1

Std.

Units

Min.1 Max.2 Min.1 Max.2

tRCKL

Input Low Delay for Global Clock

1.53

1.75

1.79

2.06

tRCKH

Input High Delay for Global Clock

1.51

1.77

1.78

2.08

tRCKMPWH

Minimum Pulse Width High for Global Clock

0.75

0.88

tRCKMPWL

Minimum Pulse Width Low for Global Clock

0.85

1.00

tRCKSW

Maximum Skew for Global Clock

0.26

0.30

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-211 • A3PE3000L Global Resource – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V

Parameter

Description

–1

Std.

Units

Min.1 Max.2 Min.1 Max.2

tRCKL

Input Low Delay for Global Clock

1.52

1.94

1.78

2.28

tRCKH

Input High Delay for Global Clock

1.49

1.96

1.76

2.30

tRCKMPWH

Minimum Pulse Width High for Global Clock

1.05

1.24

tRCKMPWL

Minimum Pulse Width Low for Global Clock

1.23

1.44

tRCKSW

Maximum Skew for Global Clock

0.47

0.55

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

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