IO96NDB2V1 datasheet(26/242 Pages) MICROSEMI

tên linh kiện	IO96NDB2V1

Giải thích chi tiết về linh kiện	ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

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ProASIC3L DC and Switching Characteristics

2-10

Revision 13

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings1

Applicable to Advanced I/O Banks

VCCI (V)

Static Power

PDC6 (mW)2

Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3

–

16.22

2.5 V LVCMOS

2.5

–

4.65

1.8 V LVCMOS

1.8

–

1.65

1.5 V LVCMOS (JESD8-11)

1.5

–

0.98

1.2 V LVCMOS

1.2

–

0.61

3.3 V PCI

3.3

–

17.64

3.3 V PCI-X

3.3

–

17.64

Differential

LVDS

2.5

2.26

0.95

LVPECL

3.3

5.72

1.63

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC6 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

VCCI (V)

Static Power

PDC6 (mW)1

Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS

3.3

–

16.23

2.5 V LVCMOS

2.5

–

4.66

1.8 V LVCMOS

1.8

–

1.64

1.5 V LVCMOS (JESD8-11)

1.5

–

0.99

1.2 V LVCMOS

1.2

–

0.58

3.3 V PCI

3.3

–

17.64

3.3 V PCI-X

3.3

–

17.64

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

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