COM20020ILJP datasheet(64/72 Pages) MICROCHIP

tên linh kiện	COM20020ILJP

Giải thích chi tiết về linh kiện	5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

PDF	72 Pages

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nhà sản xuất	MICROCHIP [Microchip Technology]

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64 / 72 page

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

Revision 12-05-06

Page 64

SMSC COM20020I Rev D

DATASHEET

nPULSE1

RXIN

t10

t11

nPULSE2

(Internal Clk)

Parameter

min

typ

max

units

t10

t11

t12

nPULSE1 Pulse Width

nPULSE1 Period

nPULSE2 Low to nPULSE1 Low

nPULSE2 High Time

nPULSE2 Low Time

nPULSE2 Period

nPULSE2 High to nTXEN High

RXIN Active Pulse Width

RXIN Period

200*

400*

100*

200*

400*

-25

nTXEN

LAST BIT

(400 nS BIT TIME)

nPULSE2 High to nTXEN Low

-25

(First Rising Edge on nPULSE2 after Last Bit Time)

nTXEN Low to first nPULSE1 Low**

650

750

t13

t12

-25

RXIN Inactive Pulse Width

t13

Beginning Last Bit Time to nTXEN High**

450

Above values are for 2.5 Mbps.

Other Data Rates are shown below.

550

TDR is the Data Rate Period

*t5, t6 = TDR/4

*t2, t7, t10 = TDR/2

*t3, t11 = TDR

**t9 =

x TDR +/- 50 nS

**t13 =

x TDR +/- 50 nS

Figure 8.12 - Backplane Mode Transmit or Receive Timing

(These signals are to and from the differential driver or the cable)

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