COM20020ILJP datasheet(62/72 Pages) MICROCHIP

62 / 72 page

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

Revision 12-05-06

Page 62

SMSC COM20020I Rev D

DATASHEET

A0-A2

VALID DATA

VALID

D0-D7

nCS

t10

Note 2

DIR

nDS

t11

t6**

Parameter

min

max

units

Address Setup to nDS Active

Address Hold from nDS Inactive

nCS Setup to nDS Active

nCS Hold from nDS Inactive

DIR Setup to nDS Active

Cycle Time (nDS

to Next Time

)**

DIR Hold from nDS Inactive

Valid Data Setup to nDS High

Data Hold from nDS High

nDS Low Width

nDS High Width

t10

t11

4TARB

30***

***: nCS may become active after control becomes active, but the data setup time will now

be 30 nS measured from the later of nCS falling or Valid Data available.

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

**Note 2: Any cycle occurring after a write to the Address Pointer Low Register

requires a minimum of 4TARB from the trailing edge of nDS to the leading edge

of the next nDS.

Write cycle for Address Pointer Low Registers occurring after an access to

Data Register requires a minimum of 5TARB from the trailing edge of nDS to

the leading edge of the next nDS.

Figure 8.10 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle

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