COM20020ILJP datasheet(57/72 Pages) MICROCHIP

57 / 72 page

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

SMSC COM20020I Rev D

Page 57

Revision 12-05-06

DATASHEET

Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle

A0-A2

VALID DATA

VALID

D0-D7

nCS

nRD

nWR

t10

Note 3

Note 2

Parameter

min

max

units

t10

5**

Address Setup to nRD Active

Address Hold from nRD Inactive

nCS Setup to nRD Active

nCS Hold from nRD Inactive

Cycle Time (nRD Low to Next Time Low)

nRD Low to Valid Data

nRD High to Data High Impedance

4TARB

40**

CASE 1: RBUSTMG bit = 0

nRD Low Width

nRD High Width

nWR

to nRD Low

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

nCS may become active after control becomes active, but the access time (t6)

will now be 45nS measured from the leading edge of nCS.

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Note 2:

Read cycle for Address Pointer Low/High Registers occurring after a read from

Data Register requires a minimum of 5TARB from the trailing edge of nRD to the

leading edge of the next nRD.

Note 3:

Read cycle for Address Pointer Low/High Registers occurring after a write to

Data Register requires a minimum of 5TARB from the trailing edge of nWR to the

leading edge of nRD.

COM20020ILJP bảng dữ liệu(PDF) 57 Page - Microchip Technology

COM20020ILJP bảng dữ liệu(HTML) 57 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

bảng dữ liệu tải về

Link URL