COM20020ILJP datasheet(55/72 Pages) MICROCHIP

55 / 72 page

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

SMSC COM20020I Rev D

Page 55

Revision 12-05-06

DATASHEET

Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle

AD0-AD2,

VALID

nCS

ALE

VALID DATA

t2,

D3-D7

DIR

t10

Note 2

t8**

nDS

t11

t12

t13

t14

Parameter

min

max

units

t10

t11

t12

t13

t14

4TARB

Address Setup to ALE Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nDS Low

Valid Data Setup to nDS High

Data Hold from nDS High

DIR Setup to nDS Active

DIR Hold from nDS Inactive

ALE High Width

ALE Low Width

nDS Low Width

nDS High Width

Cycle Time (nDS

to Next

)**

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

Any cycle occurring after a write to Address Pointer Low Register requires a

minimum of 4TARB from the trailing edge of nDS to the leading edge of the

next nDS.

Note 2:

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Write cycle for Address Pointer Low Register occurring after an access to

Data Register requires a minimum of 5TARB from the trailing edge of nDS to

the leading edge of the next nDS.

COM20020ILJP bảng dữ liệu(PDF) 55 Page - Microchip Technology

COM20020ILJP bảng dữ liệu(HTML) 55 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

bảng dữ liệu tải về

Link URL