PSD813F2 datasheet(24/128 Pages) STMICROELECTRONICS

24 / 128 page

PSD register description and address offset

PSD8XXFX

24/128

Doc ID 7833 Rev 7

PSD register description and address offset

Table 7 shows the offset addresses to the PSD registers relative to the CSIOP base

address. The CSIOP space is the 256 bytes of address that is allocated by the user to the

internal PSD registers. Table 8 provides brief descriptions of the registers in CSIOP space.

The following section gives a more detailed description.

Table 7.

I/O port latched address output assignments(1)(2)

See Section 16: I/O ports, on how to enable the Latched Address Output function.

N/A = Not Applicable

MCU

Port A

Port B

Port A (3:0)

Port A (7:4)

Port B (3:0)

Port B (7:4)

8051XA (8-bit)

N/A

Address a7-a4

Address a11-a8

N/A

80C251 (page mode)

N/A

Address a11-a8

Address a15-

a12

All other 8-bit multiplexed

Address a3-a0

Address a7-a4

Address a3-a0

Address a7-a4

8-bit non-multiplexed bus

N/A

Address a3-a0

Address a7-a4

Table 8.

name

Port A Port B Port C Port D

Other

(1)

Description

Data In

Reads port pin as input, MCU I/O input

mode

Control

Selects mode between MCU I/O or

Address Out

Data Out

Stores data for output to port pins, MCU

I/O output mode

Direction

Configures port pin as input or output

Drive Select

Configures port pins as either CMOS or

Open Drain on some pins, while selecting

high slew rate on other pins.

Input

macrocell

Reads input macrocells

Enable Out

Reads the status of the output enable to

the I/O port driver

Output

macrocells

READ – reads output of macrocells AB

WRITE – loads macrocell flip-flops

Output

macrocells

READ – reads output of macrocells BC

WRITE – loads macrocell flip-flops

Obsolete

Product(s)

- Obsolete

Product(s)

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