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PSD813F2 bảng dữ liệu(PDF) 70 Page - STMicroelectronics |
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PSD813F2 bảng dữ liệu(HTML) 70 Page - STMicroelectronics |
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70 / 128 page ![]() I/O ports PSD8XXFX 70/128 Doc ID 7833 Rev 7 Address Out Yes (A7 – 0) Yes (A7 – 0) or (A15 – 8) No No Address In Yes Yes Yes Yes Data port Yes (D7 – 0) No No No Peripheral I/O Yes No No No JTAG ISP No No Yes(1) No 1. Can be multiplexed with other I/O functions. Table 20. Port operating modes (continued) Port mode Port A Port B Port C Port D Table 21. Port operating mode settings Mode Defined in PSDabel Defined in PSD configuration Control register setting Direction register setting VM register setting JTAG Enable MCU I/O Declare pins only N/A(1) 0 1 = output, 0 = input(2) N/A N/A PLD I/O Logic equations N/A N/A (2) N/A N/A Data port (Port A) N/A Specify bus type N/A N/A N/A N/A Address Out (Port A,B) Declare pins only N/A 1 1(2) N/A N/A Address In (Port A,B,C,D) Logic for equation input macrocells N/A N/A N/A N/A N/A Peripheral I/O (Port A) Logic equations (PSEL0 & 1) N/A N/A N/A PIO bit = 1 N/A JTAG ISP(3) JTAGSEL JTAG Configuration N/A N/A N/A JTAG_Enable 1. N/A = Not Applicable 2. The direction of the port A,B,C, and D pins are controlled by the Direction register ORed with the individual output enable product term (.oe) from the CPLD AND Array. 3. Any of these three methods enables the JTAG pins on port C. Table 22. I/O port Latched address output assignments MCU Port A (PA3-PA0) Port A (PA7-PA4) Port B (PB3-PB0) Port B (PB7-PB4) 8051XA (8-Bit) N/A(1) Address a7-a4 Address a11-a8 N/A 80C251 (Page mode) N/A N/A Address a11-a8 Address a15-a12 All Other 8-Bit Multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4 8-Bit Non-Multiplexed bus N/A N/A Address a3-a0 Address a7-a4 1. N/A = Not Applicable Obsolete Product(s) - Obsolete Product(s) |
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