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PSD813F2 bảng dữ liệu(PDF) 77 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Flash in-system programmable (ISP) peripherals
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PSD813F2 bảng dữ liệu(HTML) 77 Page - STMicroelectronics

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PSD8XXFX
I/O ports
Doc ID 7833 Rev 7
77/128
Port D pins can be configured in PSDsoft Express as input pins for other dedicated
functions:
●
Address Strobe (ALE/AS, PD0)
●
CLKIN (PD1) as input to the macrocells flip-flops and APD counter
●
PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory,
SRAM and CSIOP.
Figure 29.
Port D structure
16.23
External Chip Select
The CPLD also provides three External Chip Select (ECS0-ECS2) outputs on port D pins
that can be used to select external devices. Each External Chip Select (ECS0-ECS2)
consists of one product term that can be configured active high or low. The output enable of
the pin is controlled by either the output enable product term or the Direction register (see
Figure 30).
DATA OUT
REG.
DQ
DQ
WR
WR
ECS[ 2: 0]
READ MUX
P
D
B
CPLD - INPUT
DIR REG.
DATA IN
ENABLE PRODUCT
TERM (.OE)
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI02889
Obsolete
Product(s)
- Obsolete
Product(s)



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