AMC008DFLKA datasheet(16/46 Pages) AMD

16 / 46 page

AmC0XXDFLKA

when the system samples the D7 output, it may

read either the status or valid data. Even if the device

has completed the Embedded operation and D7 has a

valid data, the data outputs on D0–D6 may be still in-

valid since the switching time for data bits (D0–D7) will

not be the same. This happens since the internal delay

paths for data bits (D0–D7) within the device are differ-

ent. The valid data will be provided only after a certain

time delay (<tOE). Please refer to Figure 5 for detailed

timing diagrams.

See Figures 3 and 5 for the Data Polling timing

speciﬁcations and diagrams.

Toggle Bit 1—D6 (D14 on Odd Byte)

The Flash Memory PC Card also features a “Toggle Bit”

as a method to indicate to the host system that the Em-

bedded algorithms are either in progress or have been

completed.

While the Embedded Program or Erase algorithm is in

progress, successive attempts to read data from the

device will result in D6 toggling between one and zero.

Once the Embedded Program or Erase algorithm is

completed, D6 will stop toggling and valid data on

D0–D7 will be read on the next successive read at-

tempt. The Toggle bit is also used for entering Erase

Suspend mode. Please refer to the section entitled

Sector Erase Suspend.

Please note that even if the device completes the Em-

bedded algorithm operation and D6 stops toggling,

data bits D0–D7 (including D6) may not be valid during

the current bus cycle. This may happen since the inter-

nal circuitry may be switching from status mode to the

Read mode. There is a time delay associated with this

mode switching. Since this time delay is always less

than tOE (OE access time), the next successive read at-

tempt (OE going low) will provide the valid data on D0–

D7. Also note that once the D6 bit has stopped toggling

and the output enable OE is held low thereafter (with-

out toggling) the data bits (D0–D7) will be valid after tOE

time delay.

See Figures 4 and 6 for the Data Polling diagram and

timing speciﬁcations.

Exceeded Timing Limits—D5

D5 will indicate if the program or erase time has ex-

ceeded the specified limits (internal pulse count). Un-

der these conditions D5 will produce a “1”. This is a fail-

ure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is

the only operating function of the device under this con-

dition. The CE circuit will partially power down the de-

vice under these conditions (to approximately 2 mA).

The OE and WE pins will control the output disable

functions as described in Table1.

The D5 failure condition will also appear if a user tries

to program a 1 to a location that is previously pro-

grammed to 0. In this case the device locks out and

never completes the Embedded Program Algorithm.

Hence, the system never reads a valid data on D7 bit

and D6 never stops toggling. Once the device has ex-

ceeded timing limits, the D5 bit will indicate a “1.”

Please note that this is not a device failure condition

since the device was incorrectly used. If this occurs, re-

set the device.

Sector Erase Timer—D3

After the completion of the initial sector erase com-

mand sequence the sector erase time-out will begin.

D3 will remain low until the time-out is complete. Data

Polling and Toggle Bit 1 are valid after the initial sector

erase command sequence.

If Data Polling or the Toggle Bit 1 indicates the device

has been written with a valid erase command, D3 may

be used to determine if the sector erase timer window

is still open. If D3 is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent

commands (other than Erase Suspend) to the device

will be ignored until the erase operation is completed

as indicated by Data Polling or Toggle Bit 1. If D3 is low

(“0”), the device will accept additional sector erase

commands. To insure the command has been accept-

ed, the system software should check the status of D3

prior to and following each subsequent sector erase

command. If D3 were high on the second status check,

the command may not have been accepted.

Refer to Table 7: Write Operation Status.

Toggle Bit II—D2

This toggle bit, along with D6, can be used to deter-

mine whether the device is in the Embedded Erase Al-

gorithm or in Erase Suspend.

Successive reads from the erasing sector will cause

D2 to toggle during the Embedded Erase Algorithm. If

the device is in the erase-suspended-read mode, suc-

cessive reads from the erase-suspended sector will

cause D2 to toggle. When the device is in the

erase-suspended-program mode, successive reads

from the byte address of the non-erase suspended

sector will indicate a logic ‘1’ at the D2 bit.

D6 is different from D2 in that D6 toggles only when the

standard Program or Erase, or Erase Suspend Pro-

gram operation is in progress. The behavior of these

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