AMC008DFLKA datasheet(27/46 Pages) AMD

27 / 46 page

AmC0XXDFLKA

WORD-WIDE PROGRAMMING AND

ERASING

Word-Wide Programming

The word-wide programming sequence will be as

usual per Table 5. The Program word command is

A0A0H. Each byte is independently programmed.

For example, if the high byte of the word indicates

the successful completion of programming via one

of its write status bits such as D15, software polling

should continue to monitor the low byte for write

completion and data veriﬁcation, or vice versa. Dur-

ing the Embedded Programming operations the de-

vice ex ecutes prog r amming pulses in 8

µs

increments. Status reads provide information on the

progress of the byte programming relative to the last

complete write pulse. Status information is automat-

ically updated upon completion of each internal

write pulse. Status information does not change

within the 8

µs write pulse width.

Word-Wide Sector Erasing

The word-wide erasing of a memory sector pair is sim-

ilar to word-wide programming. The erase word com-

mand is a 6 bus cycle command sequence per Table 5.

Each byte is independently erased and veriﬁed.

Word-wide erasure reduces total erase time when

compared to byte erasure. Each Flash memory device

in the card may erase at different rates. Therefore each

device (byte) must be veriﬁed separately.

19521D-13

Figure 12.

Embedded Algorithm Word-Wide Programming and Erasure Overview

Software polling from

memory segments

Write Embedded

Programming or Erase

command sequence to

memory segments

Completed

The Embedded Algorithm operations completely automate

the parallel programming and erase procedures by inter-

nally executing the algorithmic command sequences of

AMD’s Flashrite and Flasherase algorithms. The devices

automatically provide Write Operation Status information

with standard read operations.

See Table 5 for Program Command Sequence.

Start

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