AMC008DFLKA datasheet(15/46 Pages) AMD

15 / 46 page

AmC0XXDFLKA

The Reset command will safely reset the segment

memory to the Read mode. Memory contents are not

altered. Following any other command, write the Reset

command once to the segment. This will safely abort

any operation and reset the device to the Read mode.

The Reset is needed to terminate the auto select oper-

ation. It can be used to terminate an Erase or Sector

Erase operation, but the data in the sector or segment

being erased would then be undeﬁned.

Write Operation Status

RY/BY

Ready/Busy

The D-Series Card provides a RY/BY output pin as a

way to indicate to the host system that the Embedded

Algorithms are either in progress or has been com-

pleted. If the output is low, the card is busy with either

a program or erase operation. If the output is high, the

card is ready to accept any read/write or erase opera-

tion. When the RY/BY pin is low, the card will not accept

any additional program or erase commands with the

exception of the Erase Suspend command to the same

device pair, one can still write or erase to a different de-

vice pair. If the card is placed in an Erase Suspend

mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after

the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising

edge of the sixth WE pulse. The RY/BY pin will indicate

a busy condition during the RESET pulse. Refer to Fig-

ure 21 for a detailed timing diagram. The RY/BY pin is

pulled high in standby mode. RY/BY is best used to in-

terrupt the CPU when an erase completes. Polling is

best for byte programming.

Data Polling—D7 (D15 on Odd Byte)

The Flash Memory PC Card features Data Polling as a

method to indicate to the host system that the Embed-

ded algorithms are either in progress or completed.

While the Embedded Programming algorithm is in op-

eration, an attempt to read the device will produce the

complement of expected valid data on D7 of the ad-

dressed memory sector or memory segment. Upon

completion of the Embedded Program algorithm an at-

tempt to read the device will produce valid data on D7.

The Data Polling feature is valid after the rising edge of

the fourth WE pulse of the four write pulse sequence.

While the Embedded Erase algorithm is in operation,

D7 will read “0” until the erase operation is completed.

Upon completion of the erase operation, the data on D7

will read “1”.

The Data Polling feature is only active during the Em-

bedded Programming or Erase algorithms. Please note

that the AmC0XXDFLKA data pin (D7) may change

asynchronously while Output Enable (OE) is asserted

low. This means that the device is driving status infor-

mation on D7 at one instant of time and then the byte’s

valid data at the next instant of time. Depending on

19521D-3

Figure 2.

Embedded Programming Algorithm in Byte-Wide Mode

Write Embedded Write Command

Sequence per Table 3 or 4

Verify Byte

Yes

Data Poll Device

Yes

Increment Address

Start

Completed

Last

Address

AMC008DFLKA bảng dữ liệu(PDF) 15 Page - Advanced Micro Devices

AMC008DFLKA bảng dữ liệu(HTML) 15 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

bảng dữ liệu tải về

Link URL