AMC008DFLKA datasheet(6/46 Pages) AMD

6 / 46 page

AmC0XXDFLKA

PIN DESCRIPTION

A0–A24

Address Inputs

These inputs are internally latched during write cycles.

All address lines should be driven.

BVD1, BVD2

Battery Voltage Detect

Internally pulled-up.

CD1, CD2

Card Detect

When card detect 1 and 2 = ground the system detects

the card.

CE1, CE2

Card Enable

This input is active low. The memory card is deselected

and power consumption is reduced to standby levels

when CE is high. CE activates the internal memory

card circuitry that controls the high and low byte control

logic of the card, input buffers segment decoders, and

associated memory devices.

D0–D15

Data Input/Output

Data inputs are internally latched on write cycles. Data

outputs during read cycles. Data pins are active high.

When the memory card is deselected or the outputs

are disabled the outputs ﬂoat to tristate.

GND

Ground

No Connect

Corresponding pin is not connected.

Output Enable

This input is active low and enables the data buffers

through the card outputs during read cycles.

RY/BY

This signal is output from the card and indicates the

status of the operation in progress in the card. If this

signal is low, then the card is still busy with the current

operation. Otherwise, the card is ready to accept anew

operation.

REG

Attribute Memory Select

This input is active low and enables reading the CIS

from the EEPROM.

RESET

This input to the Card is used to reset all the Flash de-

vices inside the Card to a read mode state. If you drive

or assert RESET high during a write or erase opera-

tion, then the state of the devices for the purpose of the

operation is undefined. In order to RESET, you need to

hold the RESET pin high for 500 ns, and it takes 20

µs

before the internal circuit is RESET. When RESET is

driven high, the data bus is in a high impedance state.

VCC

PC Card Power Supply

For device operation (5.0 V

± 5%).

Write Enable

This input is active low and controls the write function

of the command register to the memory array. The

target address is latched on the falling edge of the WE

pulse and the appropriate data is latched on the rising

edge of the pulse.

Write Protect

This output is active high and disables all Card write

operations (including writes to the attribute memory).

MEMORY CARD OPERATIONS

The D-Series Flash Memory Card is organized as an

array of individual devices. Each device is 2 Mbytes in

size with thirty-two 64K byte sectors. Although the ad-

dress space is continuous, each physical device de-

fines a logical address segment size.

Erase operations can be performed on two 64KByte

sectors simultaneously. Once a memory sector or

memory segment is erased any address location may

be programmed. Flash technology allows any logical

“1” data bit to be programmed to a logical “0”. The

only way to reset bits to a logical “1” is to erase the

entire memory sector of 64K bytes or memory seg-

ment of 2 Mbytes.

Erase operations are the only operations that work on

entire memory sectors or memory segments. All other

operations such as word-wide programming are not af-

fected by the physical memory segments.

The common memory space data contents are altered

in a similar manner as writing to individual Flash mem-

ory devices. On-card address and data buffers activate

the appropriate Flash device in the memory array.

Each device internally latches address and data during

write cycles. Refer to Table 1.

Attribute memory is a separately accessed card mem-

ory space. The attribute memory space is active when

the REG pin is driven low. The Card Information Struc-

ture (CIS) describes the capabilities and specification

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