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AM79C974 bảng dữ liệu(PDF) 40 Page - Advanced Micro Devices |
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AM79C974 bảng dữ liệu(HTML) 40 Page - Advanced Micro Devices |
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40 / 153 page ![]() AMD P R E L I M I N A R Y 40 Am79C974 Master Initiated Termination There are three scenarios besides normal completion of a transaction where the Am79C974 controller will termi- nate the cycles it produces on the PCI bus. These are Preemption with and without FRAME assertion and Master Abort. Preemption When FRAME is Deasserted The Am79C974 controller can generate multiple ad- dress phases during a single bus ownership period when transferring data. FRAME is deasserted in be- tween two address phases. While FRAME is deass- erted, the central arbiter can remove GNT to the Am79C974 controller at any time to service another master. When GNT is removed, the Am79C974 control- ler will finish the current transfer and then release the bus. It will keep REQ asserted to regain bus ownership as soon as possible. 18681A-18 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT 1234567 8 ADDR BE's 0111 PAR PAR PAR DATA DEVSEL is sampled by the Am79C974 controller. Figure 14. Preemption When FRAME is Deasserted |
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