AM79C974 datasheet(39/153 Pages) AMD

39 / 153 page

P R E L I M I N A R Y

AMD

Am79C974

Target Abort

Figure 13 shows a target abort sequence. The target as-

serts

DEVSEL for one clock. It then deasserts DEVSEL

and asserts

STOP on clock 4. A target can use the target

abort sequence to indicate that it cannot service the data

transfer and that it does not want the transaction to be

retried. Additionally, the Am79C974 controller cannot

make any assumption about the success of the previous

data

transfers

the

current

transaction.

The

Am79C974 controller terminates the current transfer

with the deassertion of

FRAME on clock 5 and one clock

cycle later with the deassertion of

IRDY. It finally re-

leases the bus on clock 6.

Since data integrity is not guaranteed, the Am79C974

controller cannot recover from a target abort event. For

Ethernet, the Am79C974 controller will reset all CSR

and BCR locations to their H_RESET values. Any on-

going network activity will be stopped immediately. The

PCI configuration registers will not be cleared. For

SCSI, when target aborts,

INTA will not be asserted, but

the ABORT bit (bit 2 of the DMA status register at offset

54h), is set. For either Ethernet or SCSI a target abort

causes RTABORT (bit 12) of the status register in the

appropriate PCI configuration space to be set.

18681A-17

FRAME

CLK

IRDY

TRDY

DEVSEL

REQ

GNT

123456

DATA

0000

0111

PAR

DEVSEL is sampled by the Am79C974 controller.

STOP

ADDR

Figure 13. Target Abort

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