PCI1520PDVG4 datasheet(67/139 Pages) TI

67 / 139 page

4−6

4.9

Latency Timer Register

The latency timer register specifies the latency time for the PCI1520 in units of PCI clock cycles. When the PCI1520

is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires

before the PCI1520 transaction has terminated, then the PCI1520 terminates the transaction when its GNT is

deasserted. This register is separate for each of the two PCI1520 functions. This allows platforms to prioritize use

of the PCI bus by the two PCI1520 functions.

Bit

Name

Latency timer

Type

Default

Latency timer

Offset:

0Dh

Type:

Read/Write

Default:

00h

4.10 Header Type Register

This register returns 82h when read, indicating that the PCI1520 function 0 and 1 configuration spaces adhere to the

CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 000h to 7Fh, and 80h to FFh

is user-definable extension registers.

Bit

Name

Header type

Type

Default

Header type

Offset:

0Eh (functions 0, 1)

Type:

Read/Write

Default:

82h

4.11 BIST Register

Because the PCI1520 does not support a built-in self-test (BIST), this register returns the value of 00h when read.

Bit

Name

BIST

Type

Default

BIST

Offset:

0Fh (functions 0, 1)

Type:

Read-only

Default:

00h

PCI1520PDVG4 bảng dữ liệu(PDF) 67 Page - Texas Instruments

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