PCI1520PDVG4 datasheet(47/139 Pages) TI

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3−12

in Figure 3−9. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high

transition of SDA while SCL is in the high state, as shown in Figure 3−9. Data on SDA must remain stable during the

high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control

signals, that is, a start or a stop condition.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 3−9. Serial-Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is

unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by

the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−10

illustrates the acknowledge protocol.

SCL From

Master

123

SDA Output

By Transmitter

SDA Output

By Receiver

Figure 3−10. Serial-Bus Protocol Acknowledge

The PCI1520 is a serial bus master; all other devices connected to the serial bus external to the PCI1520 are slave

devices. As the bus master, the PCI1520 drives the SCL clock at nearly 100 kHz during bus cycles and places SCL

in a high-impedance state (zero frequency) during idle states.

Typically, the PCI1520 masters byte reads and byte writes under software control. Doubleword reads are performed

by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See

Section 3.6.3, Serial-Bus EEPROM Application, for details on how the PCI1520 automatically loads the subsystem

identification and other register defaults through a serial-bus EEPROM.

Figure 3−11 illustrates a byte write. The PCI1520 issues a start condition and sends the 7-bit slave device address

and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The slave device

acknowledges if it recognizes the address. If no acknowledgment is received by the PCI1520, then an appropriate

status bit is set in the serial-bus control and status register (PCI offset B3h, see Section 4.48). The word address byte

is then sent by the PCI1520, and another slave acknowledgment is expected. Then the PCI1520 delivers the data

byte MSB first and expects a final acknowledgment before issuing the stop condition.

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