PCI1520PDVG4 datasheet(32/139 Pages) TI

32 / 139 page

2−19

Table 2−13. CardBus PC Card Interface System Terminals (Slots A and B)

TERMINAL

NUMBER

I/O

DESCRIPTION

NAME

SLOT A†

SLOT B‡

I/O

DESCRIPTION

NAME

PDV

GHK

PDV

GHK

CCLK

115

M14

P06

CardBus clock. CCLK provides synchronous timing for all transactions on the

CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO,

CCD2, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all

timing parameters are defined with the rising edge of this signal. CCLK operates at

the PCI bus clock frequency, but it can be stopped in the low state or slowed down

for power savings.

CCLKRUN

142

H15

R09

I/O

CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase

in the CCLK frequency, and by the PCI1520 to indicate that the CCLK frequency is

going to be decreased.

CRST

126

L15

W05

CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and

signals to a known state. When CRST is asserted, all CardBus PC Card signals are

placed in a high-impedance state, and the PCI1520 drives these signals to a valid

logic level. Assertion can be asynchronous to CCLK, but deassertion must be

synchronous to CCLK.

† Terminal name for slot A is preceded with A_. For example, the full name for terminals 115 and M14 is A_CCLK.

‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P06 is B_CCLK.

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