APA600 datasheet(28/178 Pages) ACTEL

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ProASICPLUS Flash Family FPGAs

2- 18

v5.9

PLL Electrical Specifications

Parameter

Value TJ ≤ –40°C

Value TJ > –40°C

Notes

Frequency Ranges

Reference Frequency fIN (min.)

2.0 MHz

1.5 MHz

Clock conditioning circuitry (min.) lowest input

frequency

Reference Frequency fIN (max.)

180 MHz

Clock conditioning circuitry (max.) highest input

frequency

OSC Frequency fVCO (min.)

24 MHz

Lowest output frequency voltage controlled

oscillator

OSC Frequency fVCO (max.)

180

180 MHz

Highest output frequency voltage controlled

oscillator

Clock Conditioning Circuitry fOUT (min.)

fIN ≤ 40 = 18 MHz

fIN > 40 = 16 MHz

6 MHz

Lowest output frequency clock conditioning

circuitry

Clock Conditioning Circuitry fOUT (max.) 180

180 MHz

Highest output frequency clock conditioning

circuitry

Acquisition Time from Cold Start

Acquisition Time (max.)

μs

μsf

VCO ≤ 40 MHz

Acquisition Time (max.)

μs

μsf

VCO > 40 MHz

Long Term Jitter Peak-to-Peak Max.*

Temperature

Frequency MHz

fVCO<

10<fV

CO<60

fVCO

>60

25°C (or higher)

±1%

±2%

±1% Jitter(ps) = Jitter(%)*period

For example:

Jitter in picoseconds at 100 MHz

= 0.01 * (1/100E6) = 100 ps

0°C

±1.5% ±2.5% ±1%

–40°C

±2.5% ±3.5% ±1%

–55°C

±2.5% ±3.5% ±1%

Power Consumption

Analog Supply Power (max.*)

6.9 mW per PLL

Digital Supply Current (max.)

μW/MHz

Duty Cycle

50% ±0.5%

Input Jitter Tolerance

5% input period (max.

5 ns)

Maximum jitter allowable on an input

clock to acquire and maintain lock.

Note: *High clock frequencies (>60 MHz) under typical setup conditions

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