APA600 datasheet(77/178 Pages) ACTEL

77 / 178 page

ProASICPLUS Flash Family FPGAs

v5.9

2-67

Asynchronous FIFO Read

Note: The plot shows the normal operation status.

Figure 2-40 • Asynchronous FIFO Read

Table 2-63 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial

TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol txxx

Description

Min.

Max.

Units

Notes

ERDH, FRDH,

THRDH

Old EMPTY, FULL, EQTH, & GETH valid hold

time from RB

↑

0.5

Empty/full/thresh are invalid from the end

of hold until the new access is complete

ERDA

New EMPTY access from RB

↑

3.01

FRDA

FULL

↓ access from RB ↑

3.01

ORDA

New DO access from RB

↓

7.5

ORDH

Old DO valid from RB

↓

3.0

RDCYC

Read cycle time

7.5

RDWRS

↑, clearing EMPTY, setup to

↓

3.02

Enabling the read operation

1.0

Inhibiting the read operation

RDH

RB high phase

3.0

Inactive

RDL

RB low phase

3.0

Active

RPRDA

New RPE access from RB

↓

9.5

RPRDH

Old RPE valid from RB

↓

4.0

THRDA

EQTH or GETH access from RB

↑

4.5

Notes:

1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.

2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns.

RB = (RDB+RBLKB)

RPE

RDATA

EMPTY

EQTH, GETH

FULL

(Empty inhibits read)

Cycle Start

tRDWRS

tERDH, tFRDH

tERDA, tFRDA

tTHRDH

tORDH

tRPRDH

tORDA

tRPRDA

tRDL

tRDH

tRPRDA

tRDL

tRDCYC

tRDH

tTHRDA

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