APA600 datasheet(72/178 Pages) ACTEL

72 / 178 page

ProASICPLUS Flash Family FPGAs

2- 62

v5.9

Asynchronous Write and Synchronous Read to the Same Location

Note: *New data is read if WB

↓ occurs before setup time. The stored data is read if WB ↓ occurs after hold time. The plot shows the

normal operation status.

Figure 2-35 • Asynchronous Write and Synchronous Read to the Same Location

Table 2-59 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial

TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol txxx

Description

Min.

Max.

Units

Notes

CCYC

Cycle time

7.5

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

WBRCLKS

↓ to RCLKS ↑ setup time

–0.1

WBRCLKH

↓ to RCLKS ↑ hold time

7.0

OCH

Old DO valid from RCLKS

↑

3.0

OCA/OCH

displayed

for

Access Timed Output

OCA

New DO valid from RCLKS

↑

7.5

DWRRCLKS

DI to RCLKS

↑ setup time

DWRH

DI to WB

↑ hold time

1.5

Notes:

1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.

2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write

signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be

read.

3. A setup or hold time violation will result in unknown output data.

WB = {WRB + WBLKB}

RCLKS

BRCLKH

New Data*

Last Cycle Data

WRCKS

OCH

OCA

DWRRCLK

DWRH

CCYC

CMH

CML

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