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DM163006 bảng dữ liệu(PDF) 82 Page - Microchip Technology

tên linh kiện DM163006
Giải thích chi tiết về linh kiện  High-Performance ROM-less Microcontrollers
PDF  320 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DM163006 bảng dữ liệu(HTML) 82 Page - Microchip Technology

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PIC18C601/801
DS39541A-page 82
Advance Information
 2001 Microchip Technology Inc.
6.3.4
16-BIT EXTERNAL TABLE WRITE
(BYTE SELECT MODE)
This mode allows Table Writes to word-wide external
memories that have byte selection capabilities. This
generally includes word-wide FLASH devices and
word-wide static RAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD<15:0> bus.
The WRH line is strobed for each write cycle and the
WRL line is unused. The BA0 or UB or UL lines are
used to select the byte to be written, based on the LSb
of the TBLPTR.
JEDEC standard flash memories will require a I/O port
line to become a BYTE/WORD input signal and will
use the BA0 signal as a byte address. JEDEC stan-
dard static RAM memories will use the UB or UL sig-
nals to select the byte.
Figure 6-10 shows the timing associated with this mode.
FIGURE 6-10:
TBLWT
EXTERNAL INTERFACE TIMING (16-BIT BYTE SELECT MODE)
Q2
Q1
Q3 Q4
Q2
Q1
Q3 Q4
Q2
Q1
Q3 Q4
ALE
OE
WRH
WRL
BA0
Opcode Fetch
Opcode Fetch
Opcode Fetch
TBLWT*+
TBLWT* Cycle1
MOVLW 55h
from 007554h
Q2
Q1
Q3 Q4
TBLWT 56h
to 199E66h
from 00755Ah
Memory
Cycle
Instruction
Execution
INST(PC-2)
TBLWT* Cycle2
MOVWF TABLAT
from 007556h
Q2
Q1
Q3 Q4
Q2
Q1
Q3 Q4
TBLWT 92h
to 199E67h
TBLWT*+ Cycle1 TBLWT*+ Cycle2
UB
LB
Opcode Fetch
TBLWT*
from 007558h
MOVWF
’1’
A<19:16>
3AAAh
AD<15:0>
0h
0h
000Dh
Ch
CF33h
5656h
3AABh
6FF4h
3AACh
000Ch
0h
0h
3AADh
0E55h
CF33h
9292h
Ch



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