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DM163006 bảng dữ liệu(PDF) 36 Page - Microchip Technology |
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DM163006 bảng dữ liệu(HTML) 36 Page - Microchip Technology |
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36 / 320 page  PIC18C601/801 DS39541A-page 36 Advance Information 2001 Microchip Technology Inc. CCPR2H 601 801 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 601 801 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 601 801 --00 0000 --00 0000 --uu uuuu TMR3H 601 801 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 601 801 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 601 801 0000 0000 uuuu uuuu uuuu uuuu SPBRG 601 801 xxxx xxxx uuuu uuuu uuuu uuuu RCREG 601 801 xxxx xxxx uuuu uuuu uuuu uuuu TXREG 601 801 xxxx xxxx uuuu uuuu uuuu uuuu TXSTA 601 801 0000 -01x 0000 -01u uuuu -uuu RCSTA 601 801 0000 000x 0000 000u uuuu uuuu IPR2 601 801 -1-- 1111 -1-- 1111 -u-- uuuu PIR2 601 801 -1-- 0000 -1-- 0000 -u-- uuuu(1) PIE2 601 801 -1-- 0000 -1-- 0000 -u-- uuuu IPR1 601 801 1111 1111 1111 1111 uuuu uuuu 601 801 -111 1111 -111 1111 -uuu uuuu PIR1 601 801 0000 0000 0000 0000 uuuu uuuu(1) 601 801 -000 0000 -000 0000 -uuu uuuu(1) PIE1 601 801 0000 0000 0000 0000 uuuu uuuu 601 801 -000 0000 -000 0000 -uuu uuuu MEMCON 601 801 0000 --00 0000 --00 uuuu --uu TRISJ 601 801 1111 1111 1111 1111 uuuu uuuu TRISH 601 801 1111 1111 1111 1111 uuuu uuuu TRISG 601 801 ---1 1111 ---1 1111 ---u uuuu TRISF 601 801 1111 1111 1111 1111 uuuu uuuu TRISE 601 801 1111 1111 1111 1111 uuuu uuuu TRISD 601 801 1111 1111 1111 1111 uuuu uuuu TRISC 601 801 1111 1111 1111 1111 uuuu uuuu TRISB 601 801 1111 1111 1111 1111 uuuu uuuu TRISA 601 801 --11 1111 --11 1111 --uu uuuu LATG 601 801 ---x xxxx ---u uuuu ---u uuuu LATF 601 801 xxxx xxxx uuuu uuuu uuuu uuuu LATE 601 801 xxxx xxxx uuuu uuuu uuuu uuuu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset MCLR Reset WDT Reset Reset Instruction Stack Over/Underflow Reset Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition, r = reserved, maintain ‘0’ Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (00008h or 00018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are updated with the current value of the PC. The SKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: This is not a physical register. It is an indirect pointer that addresses another register. The contents returned is the value contained in the addressed register. |
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