DM163006 datasheet(29/320 Pages) MICROCHIP

29 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 29

PIC18C601/801

3.0

RESET

PIC18C601/801 devices differentiate between various

kinds of RESET:

Power-on Reset (POR)

MCLR Reset during normal operation

MCLR Reset during SLEEP

Watchdog Timer (WDT) Reset during normal

operation

RESET

Instruction

Stack Full Reset

Stack Underflow Reset

Most registers are unaffected by a RESET. Their status

is unknown on POR and unchanged by all other

RESETS. The other registers are forced to a “RESET”

state on Power-on Reset, MCLR, WDT Reset, MCLR

Reset during SLEEP, and by the RESET instruction.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD

and POR, are set or cleared differently in different

RESET situations, as indicated in Table 3-2. These bits

are used in software to determine the nature of the

RESET. See Table 3-3 for a full description of the

RESET states of all registers.

A simplified block diagram of the on-chip RESET circuit

is shown in Figure 3-1.

PIC18C601/801 has a MCLR noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

A WDT Reset does not drive MCLR pin low.

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF THE ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

OSC1

VDD Rise

Detect

OST/PWRT

On-chip

RC OSC(1)

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST(2)

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

WDT

Module

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