DM163006 datasheet(25/320 Pages) MICROCHIP

25 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 25

PIC18C601/801

OSCCON REGISTER

2.6.2

OSCILLATOR TRANSITIONS

PIC18C601/801 devices contain circuitry to prevent

"glitches" when switching between oscillator sources.

Essentially, the circuitry waits for eight rising edges of

the clock source that the processor is switching to.

This ensures that the new clock source is stable and

that its pulse width will not be less than the shortest

pulse width of the two clock sources.

A timing diagram indicating the transition from the main

oscillator to the Timer1 oscillator is shown in Figure 2-6.

The Timer1 oscillator is assumed to be running all the

time. After the SCS0 bit is set, the processor is frozen

at the next occurring Q1 cycle. After eight synchroniza-

tion cycles are counted from the Timer1 oscillator, oper-

ation resumes. No additional delays are required after

the synchronization cycles.

The sequence of events that takes place when switch-

ing from the Timer1 oscillator to the main oscillator will

depend on the mode of the main oscillator. In addition

to eight clock cycles of the main oscillator, additional

delays may take place.

If the main oscillator is configured for an external crys-

tal (HS, LP), the transition will take place after an oscil-

lator start-up time (TOST) has occurred. A timing

diagram indicating the transition from the Timer1 oscil-

lator to the main oscillator for HS and LP modes is

shown in Figure 2-7.

U-0

R/W-0

—

LOCK

PLLEN

SCS1

SCS0

bit 7

bit 0

bit 7-4

Unimplemented: Read as '0'

bit 3

LOCK: Phase Lock Loop Lock Status bit

= Phase Lock Loop output is stable as system clock

= Phase Lock Loop output is not stable and cannot be used as system clock

bit 2

PLLEN: Phase Lock Loop Enable bit

= Enable Phase Lock Loop output as system clock

= Disable Phase Lock Loop

bit 1

SCS1: System Clock Switch bit 1

When PLLEN and LOCK bit are set:

= Use PLL output

= Use primary oscillator/clock input pin

When PLLEN bit or LOCK bit is cleared:

Bit is forced clear

bit 0

SCS0: System Clock Switch bit 0

When T1OSCEN bit is set:

= Switch to Timer1 oscillator/clock pin

= Use primary oscillator/clock input pin

When T1OSCEN is cleared:

Bit is forced clear

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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