ADSP-21486KSWZ-2AB datasheet(25/68 Pages) AD

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25 / 68 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. B

Page 25 of 68

March 2013

Clock Signals

The ADSP-2148x can use an external clock or a crystal. See the

CLKIN pin description in Table 11 on Page 14. Programs can

configure the processor to use its internal clock generator by

connecting the necessary components to CLKIN and XTAL.

Figure 7 shows the component connections used for a crystal

operating in fundamental mode. Note that the clock rate is

achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

Figure 7. Recommended Circuit for

Fundamental Mode Crystal Operation

22pF

XTAL

CLKIN

22pF

25MHz

TYPICAL VALUES

ADSP-2148x

CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE

POWER. REFER TO CRYSTAL MANUFACTURER’S

SPECIFICATIONS.

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