EP3SE110 datasheet(22/341 Pages) ALTERA

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

Electrical Characteristics

Stratix III Device Handbook, Volume 2

Altera Corporation

Power Consumption

Altera offers two ways to estimate power for a design: the Excel-based Early Power

Estimator (EPE) and the Quartus II PowerPlay Power Analyzer feature.

The interactive Excel-based Early Power Estimator is typically used prior to designing

the FPGA in order to get a magnitude estimate of the device power. The Quartus II

PowerPlay Power Analyzer

provides estimation based on the specifics of the design

after place-and-route is complete. The PowerPlay Power Analyzer can apply a

combination of user-entered, simulation-derived, and estimated signal activities

which, when combined with detailed circuit models, can yield very accurate power

estimation.

Refer to Table 1–4 on page 1–5 for supply current estimates for VCCPGM and VCC_CLKIN.

Use the EPE and PowerPlay Power Analyzer for current estimates of remaining

power supplies.

f For more information about power estimation tools, refer to the PowerPlay Early Power

Estimator User Guide For Stratix III FPGAs and the PowerPlay Power Analysis chapter in

the Quartus II Handbook.

2.5 V LVDS

(Column I/O)

2.375

2.5

2.625

0.1

CM = 1.25

—

0.05

(6)

max 700

Mbps

1.8

(6)

0.247

—

0.6

1.0

1.25

1.5

2.375

2.5

2.625

0.1

CM = 1.25

—

1.05

(6)

max > 700

Mbps

1.55

(6)

0.247

—

0.6

1.0

1.25

1.5

RSDS

(Row I/O)

2.375

2.5

2.625

0.1

CM = 1.25

—

0.3

—

1.4

0.1

0.2

0.6

0.5

1.2

1.4

RSDS

(Column I/O)

2.375

2.5

2.625

0.1

CM = 1.25

—

0.3

—

1.4

0.1

0.2

0.6

0.5

1.2

1.5

Mini-LVDS

(Row I/O)

2.375

2.5

2.625

0.2

—

0.6

0.4

—

1.325

0.25

—

0.6

0.5

1.2

1.4

Mini-LVDS

(Column I/0)

2.375

2.5

2.625

0.2

—

0.6

0.4

—

1.325

0.25

—

0.6

0.5

1.2

1.5

LVPECL

(3)

2.375

(5)

2.5

(5)

2.625

(5)

0.3

—

0.6

max 700

Mbps

1.8

(4)

——

—

2.375

(5)

2.5

(5)

2.625

(5)

0.3

—

1.0

max > 700

Mbps

1.6

(4)

——

—

Notes to Table 1–18:

(1) The minimum V

ID value is applicable over the entire common mode range, VCM.

(2) RL range: 90

RL  110 .

(3) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in column I/O use

VCC_CLKIN that must be powered by 2.5 V. Differential clock inputs in row I/O banks are powered by VCCPD.

(4) The receiver voltage input range for the data rate when Dmax > 700 Mbps is 0.85 V VIN 1.75 V.

The receiver voltage input range for the data rate when Dmax 700 Mbps is 0.45 V VIN 1.95 V.

(5) Power supply for the column I/O LVPECL differential clock input buffer is V

CC_CLKIN.

(6) The receiver voltage input range for the data rate when Dmax > 700 Mbps is 1.0 V VIN 1.6 V.

The receiver voltage input range for the data rate when Dmax 700 Mbps is zero V VIN 1.85 V.

Table 1–18. Differential I/O Standard Specifications (Part 2 of 2)

I/O

Standard

CCIO (V)

ID (V) (1)

ICM(DC) (V)

OD (V) (2)

OCM (V) (2)

Min

Typ

Max

Min

Condition

Max

Min

Condition

Max

Min

Typ

Max

Min

Typ

Max

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