M68HC08 datasheet(99/332 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

System Integration Module (SIM)

Figure 8-1. SIM Block Diagram

Table 8-1. SIM Module Signal Name Conventions

Signal Name

Description

OSCDCLK

Clock doubler output which has twice the frequency of OSC1 from the oscillator

OSCOUT

The OSCDCLK frequency divided by two. This signal is again divided by two in the

SIM to generate the internal bus clocks.

(Bus clock = OSCDCLK ÷ 4 = OSCXCLK ÷ 2)

IAB

Internal address bus

IDB

Internal data bus

PORRST

Signal from the power-on reset module to the SIM

IRST

Internal reset signal

R/W

Read/write signal

STOP/WAIT

CLOCK

CONTROL

CLOCK GENERATORS

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

INTERRUPT CONTROL

AND PRIORITY DECODE

MODULE STOP

MODULE WAIT

CPU STOP (FROM CPU)

CPU WAIT (FROM CPU)

SIMOSCEN (TO OSCILLATOR)

OSCOUT (FROM OSC)

INTERNAL CLOCKS

MASTER

RESET

CONTROL

RESET

PIN LOGIC

ILLEGAL OPCODE (FROM CPU)

ILLEGAL ADDRESS (FROM ADDRESS

MAP DECODERS)

COP TIMEOUT (FROM COP MODULE)

INTERRUPT SOURCES

CPU INTERFACE

RESET

CONTROL

SIM

COUNTER

COP CLOCK

OSCDCLK (FROM OSC)

÷ 2

USB RESET (FROM USB MODULE)

LVI RESET (FROM LVI MODULE)

VDD

INTERNAL

PULL-UP

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