M68HC08 datasheet(101/332 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

System Integration Module (SIM)

101

8.3.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency

divided by two.

8.3.2 Clock Startup from POR or LVI Reset

When the power-on reset (POR) module or the low-voltage inhibit

module generates a reset, the clocks to the CPU and peripherals are

inactive and held in an inactive phase until after the 4096 OSCDCLK

cycle POR timeout has completed. The RST pin is driven low by the SIM

during this entire period. The IBUS clocks start upon completion of the

timeout.

8.3.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows

OSCDCLK to clock the SIM counter. The CPU and peripheral clocks do

not become active until after the stop delay timeout. This timeout is

selectable as 4096 or 2048 OSCDCLK cycles. (See 8.7.2 Stop Mode.)

In wait mode, the CPU clocks are inactive. The SIM also produces two

sets of clocks for other modules. Refer to the wait mode subsection of

each module to see if the module is active or inactive in wait mode.

Some modules can be programmed to be active in wait mode.

8.4 Reset and System Initialization

The MCU has the following reset sources:

•

Power-on reset module (POR)

•

External reset pin (RST)

•

Computer operating properly module (COP)

•

Illegal opcode

•

Illegal address

•

Universal serial bus module (USB)

•

Low-voltage inhibit module (LVI)

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