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LM5039 bảng dữ liệu(PDF) 21 Page - Texas Instruments

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tên linh kiện LM5039
Giải thích chi tiết về linh kiện  105V / 2A Half-Bridge Gate Drivers, Synchronous Rectifier Control Outputs with Programmable Delays
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LM5039 bảng dữ liệu(HTML) 21 Page - Texas Instruments

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+
-
STANDBY
OFF
5.0V
0.4V
1.25V
23 PA
LM5039
-
+
R1
R2
VIN
UVLO
R2 =
1.25 x R1
VPWR -1.25
VHYS
23 PA
R1 =
LM5039
www.ti.com
SNVS621D – FEBRUARY 2010 – REVISED MARCH 2013
When choosing the RDLY value, worst case propagation delays and component tolerances should be considered
to assure that there is never a time where both SR MOSFETs are enabled AND one of the primary side
MOSFETs is enabled. The time period T1 should be set so that the SR MOSFET has turned off before the
primary MOSFET is enabled. Conversely, T1 and T2 should be kept as low as tolerances allow to optimize
efficiency. The SR body diode conducts during the time between the SR MOSFET turns off and the power
transformer begins supplying energy. Power losses increase when this happens since the body diode voltage
drop is many times higher than the MOSFET channel voltage drop. The interval of body diode conduction can be
observed with an oscilloscope as a negative 0.7V to 1.5V pulse at the SR MOSFET drain.
UVLO Divider Selection
A dedicated comparator connected to the UVLO pin is used to detect under-voltage condition. When the UVLO
pin voltage is below 0.4V, the controller is in a low current shutdown mode. For a UVLO pin voltage greater than
0.4V but less than 1.25V the controller is in standby mode. Once the UVLO pin voltage is greater than 1.25V, the
controller is fully enabled. When the UVLO pin voltage rises above 1.25V threshold, an internal 23µA current
source is activated thus providing threshold hysteresis. The 23µA current source is deactivated when the voltage
at the UVLO pin falls below 1.25V. Resistance values for R1 and R2 can be determined from the following
equations:
where
VPWR is the desired turn-on voltage
VHYS is the desired UVLO hysteresis at VPWR
(10)
For example, if the LM5039 is to be enabled when VPWR reaches 33V, and disabled when VPWR is decreased
to 30V, R1 should be 130k
Ω, and R2 should be 5.11kΩ. The voltage at the UVLO pin should not exceed 7V at
any time. Be sure to check both the power and voltage rating (0603 resistors can be rated as low as 50V) for the
selected R1 resistor. To maintain the threshold’s accuracy, a resistor tolerance of 1% or better is recommended.
Remote configuration of the controller’s operational modes can be accomplished with open drain device(s)
connected to the UVLO pin as shown in Figure 22.
Figure 22. Basic UVLO Configuration
Copyright © 2010–2013, Texas Instruments Incorporated
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