AD9979BCPZ datasheet(4/56 Pages) AD

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AD9979

Rev. C | Page 4 of 56

TIMING SPECIFICATIONS

CL = 20 pF, AVDD = DVDD = 1.8 V, fCLI = 65 MHz, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Comments

MASTER CLOCK (CLI)

See Figure 15

CLI Clock Period

tCONV

15.38

CLI High/Low Pulse Width

tADC

6.9

7.7

8.9

Delay from CLI Rising Edge to Internal

Pixel Position 0

tCLIDLY

AFE

SHP Rising Edge to SHD Rising Edge

tS1

6.9

7.7

8.5

See Figure 19

AFE Pipeline Delay

Cycles

See Figure 20

CLPOB Pulse Width (Programmable)1

tCOB

Pixels

HD Pulse Width

tCONV

VD Pulse Width

1 HD period

SERIAL INTERFACE

See Figure 56

Maximum SCK Frequency

fSCLK

MHz

SL to SCK Setup Time

tLS

SCK to SL Hold Time

tLH

SDATA Valid to SCK Rising Edge Setup

tDS

SCK Rising Edge to SDATA Hold

tDH

H-COUNTER RESET SPECIFICATIONS

See Figure 53

HD Pulse Width

tCONV

VD Pulse Width

1 HD period

VD Falling Edge to HD Falling Edge

tVDHD

VD period − tCONV

HD Falling Edge to CLI Rising Edge

tHDCLI

tCONV − 2

CLI Rising Edge to SHPLOC (Internal

Sample Edge)

tCLISHP

tCONV − 2

TIMING CORE SETTING RESTRICTIONS

Inhibited Region for SHP Edge Location2

(See Figure 19)

tSHPINH

64/0

Edge location

Inhibited Region for SHP or SHD with

Respect to H-Clocks(See Figure 19)3, 4, 5, 6

RETIME = 0, MASK = 0

tSHDINH

H × NEGLOC − 15

H × NEGLOC − 0

Edge location

RETIME = 0, MASK = 1

tSHDINH

H × POSLOC − 15

H × POSLOC − 0

Edge location

RETIME = 1, MASK = 0

tSHPINH

H × NEGLOC − 15

H × NEGLOC − 0

Edge location

RETIME = 1, MASK = 1

tSHPINH

H × POSLOC − 15

H × POSLOC − 0

Edge location

Inhibited Region for DOUTPHASE Edge

Location (See Figure 19)

tDOUTINH

SHDLOC + 0

SHDLOC + 15

Edge location

1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

2 Only applies to slave mode operation. The inhibited area for SHP is needed to meet the timing requirements for tCLISHP for proper H-counter reset operation.

3 When 0x34[2:0] HxBLKRETIME bits are enabled, the inhibit region for SHD location changes to inhibit region for SHP location.

4 When sequence register 0x09[23:21] HBLK masking registers are set to 0, the H-edge reference becomes H × NEGLOC.

5 The H-clock signals that have SHP/SHD inhibit regions depends on the HCLK mode: Mode 1 = H1, Mode 2 = H1, H2, and Mode 3 = H1, H3.

6 These specifications apply when H1POL, H2POL, RGPOL, and HLPOL are all set to 1 (default setting).

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