AD9979BCPZ datasheet(35/56 Pages) AD

35 / 56 page

AD9979

Rev. C | Page 35 of 56

APPLICATIONS INFORMATION

RECOMMENDED POWER-UP SEQUENCE

When the AD9979 is powered up, the following sequence is

recommended (refer to Figure 52 for each step).

Turn on the power supplies for the AD9979 and apply CLI

clock. There is no required order for bringing up each supply.

Although the AD9979 contains an on-chip, power-on reset,

a software reset of the internal registers is recommended.

Write 1 to SW_RST (Address 0x10, Bit [0], which resets all

the internal registers to their default values. This bit is self-

clearing and automatically resets back to 0.

Write to the desired registers to configure high speed

timing and horizontal timing. Note that all TESTMODE

registers must be written as described in the register maps.

To place the part into normal power operation, write 0 to

STANDBY (Address 0x00, Bits[1:0])and REFBUF_PWRDN

(Address 0x00, Bit 2).

The Precision Timing core must be reset by writing 1 to

TGCORE_RST (Address 0x14, Bit 0). This starts the

internal timing core operation.

Write 1 to OUT_CONTROL (Address 0x11, Bit 0).

The next VD/HD falling edge allows register updates to occur,

including OUT_CONTROL (Address 0x11, Bit [0]), which

enables all clock outputs.

POWER

SUPPLIES

CLI

(INPUT)

SERIAL

WRITES

(INPUT)

HIGH-Z BY

DEFAULT

CLOCKS ACTIVE WHEN OUT_CONTROL

1ST FIELD

AD9979 SUPPLIES

HORIZONTAL

CLOCKS

H1, H3, RG

H2, H4

Figure 52. Recommended Power-Up Sequence

AD9979BCPZ bảng dữ liệu(PDF) 35 Page - Analog Devices

AD9979BCPZ bảng dữ liệu(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL